32-bit Pipelined MIPS Processor & Embedded Systems

To gain a rigorous understanding of computer microarchitecture, I designed and synthesized a 5-stage pipelined MIPS processor entirely in VHDL. Architected from the gate level up, the CPU implements Instruction Fetch, Decode, Execute, Memory, and Writeback stages. I developed the ALU, control units, hazard detection, and forwarding logic to support full data flow for R-type, I-type, and J-type instructions. The design was verified via ModelSim testbenches, successfully executing machine code at a target 50MHz clock frequency on an Intel Cyclone V FPGA.

Designed a complex traffic control system utilizing finite state machines (FSM) synthesized onto the Altera Cyclone V FPGA. The system incorporated sensor-driven dynamic timing and emergency vehicle interrupts. Validated state transitions using rigorous timing analysis and oscilloscope verification, demonstrating strong proficiency in Register-Transfer Level (RTL) design and digital logic.

Developed highly optimized, interrupt-driven firmware on the DE10 Standard's ARM Cortex-A9 processor. Employed a mixed-language architecture: high-level C for application logic and hand-optimized ARM Assembly for Interrupt Service Routines (ISRs) to minimize context-switching overhead. This required direct manipulation of hardware registers, priority-based interrupt vectoring, and strict mitigation of race conditions. These are essential skills for embedded software engineering in autonomous systems.